I am using a library which has a sample application. The sample makefile contains
g++ -Wl,--no-as-needed -o Example $<
rm -f SampleApp11
$< the name of the related file that caused the action.
this is a suffix replacement rule for building .o's from .c's
it uses automatic variables $<: the name of the prerequisite of
the rule(a .c file) and $@: the name of the target of the rule (a .o file)
(see the gnu make manual section about automatic variables)
$(CC) $(CFLAGS) $(INCLUDES) -c $< -o $@
This is actually nothing to do with the compiler, its part of the
Makefile syntax and it is substituted before the compiler is run.
In your example it's the first dependency (file) after the
all: target -
The basic function of the
Makefile is to create a target if a dependency changes:
target: dependency.cpp rule to create target (using dependency.cpp)
$< is the input to the compiler and
$@ is the output.
It's sort of as if it was this (not a valid
$@: $< g++ -o $@ $<
The way I remember them is
@ resembles a target (as in target practice) and
< resembles an arrow. So I imagine an arrow pointing to a target:
@ <-------- (think "Robin Hood")