My C code has various files having statements that I want to execute only if a macro is defined. I have two files each having the following code:
make -C /lib/modules/$(shell uname -r )/build M=$(PWD) modules $(CFLAGS)
make all CFLAGS=SOME_MACRO=10
make all CFLAGS=SOME_MACRO
make: *** No rule to make target `SOME_MACRO'. Stop.
make: Leaving directory `/X/Y/Z'
make: *** [default] Error 2
make all CFLAGS=-DSOME_MACRO=10
The third form is correct (
make all CFLAGS=-DSOME_MACRO=10 or just
make all CFLAGS=-DSOME_MACRO). But the make file that you are calling has to actually use that
Make's implicit rules for compiling an executable or object c file will use
CFLAGS, but we can't tell whether it is being invoked or overridden without seeing either the content of that makefile or the output from make.
The output from make should show the build commands. The implicit rule for making a
.o from a
.c file is
$(CC) $(CPPFLAGS) $(CFLAGS) -c so you should see something like
cc -DSOME_MACRO=2 -DFOO=99 -c -o x.o x.c given you compiling an object file, and similar if you compiling a executable.
Also make sure your cleaning you project properly
make clean. And make sure the clean is actually recursive (i.e. cleans you "modules" project too)...
Edit: Oh yeah ... as @nneonneo's answer points out you also have an error in recursive the make call which is definitely an issue (I figured you were running the 2nd make command directly to debug the problem..). The above may still apply.