Keita Keita - 8 days ago 4
C Question

Makefile syntax: what is $(RM)?

I saw the following Makefile online (here):

hello:

clean:
$(RM) hello


When there is a hello.c file in the same directory with the Makefile,
make
command in Terminal builds
hello
executable. When
make clean
is run,
hello
executable is removed by
rm -f hello
instead. So,
$(RM) hello
means
rm -f hello
here.


  • What does $(FOO) mean? Is it a special syntax of Makefile, or something bash command?

  • Can I run other commands as well as $(RM), like $(PWD)?


Answer

It's a Makefile variable. There're explicit variable (which is defined inside Makefile) or implicit variable (defined by make, can be override by you).

The list of implicit variables can be found by:

make -p

some of the most common variables can be found at: 10.3 Variables Used by Implicit Rules

You can expand variable by $(NAME) or ${NAME}