I need to automate a variable alignment in my Makefile. My Makefile's full file path is:
BRANCH_NAME= $(shell cd ../.. && basename "$PWD" && cd projectname/modulename)
$ has a special meaning to Make, so if you want to pass that up to shell you have to "escape" it. In case of Make, you escape the dollar sign by doubling. So you have to use
Also, what you are doing is not really the best way - it is always best to avoid the shell and use Make functionality if possible. In your case, the best way to do what you want is this:
BUILD_DIR := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))/../../build)
You have to put the above line in the makefile in question, near the top, so that it is before you
include any other makefiles.