FabienM FabienM - 9 months ago 59
Scala Question

Is there a simple example of how to generate verilog from Chisel3 module?

I'm looking for a simple howto to convert a simple Chisel3 module in Verilog.

I take Gcd source code given on official web page of chisel.

import chisel3._

class GCD extends Module {
val io = IO(new Bundle {
val a = Input(UInt.width(32))
val b = Input(UInt.width(32))
val e = Input(Bool())
val z = Output(UInt.width(32))
val v = Output(Bool())
val x = Reg(UInt.width( 32))
val y = Reg(UInt.width( 32))
when (x > y) { x := x -% y }
.otherwise { y := y -% x }
when (io.e) { x := io.a; y := io.b }
io.z := x
io.v := y === 0.U

I can't find a how to write a build.sbt and class instantiation for converting it in Verilog.

Answer Source

Thank you for your interest in Chisel! We generally encourage people to use our chisel-template repo as a starting point for Chisel3 projects: https://github.com/ucb-bar/chisel-template

If you want to do the most barebones possible thing. Create this build.sbt and put it in the root directory for your project.

scalaVersion := "2.11.8"

resolvers ++= Seq(

libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.0-SNAPSHOT"

Put the above GCD source could in GCD.scala and add the following to the file:

object GCDDriver extends App {
  chisel3.Driver.execute(args, () => new GCD)

You can then generate the Verilog by running: sbt "run-main GCDDriver". Currently, the default output directory is test_run_dir, but I believe it should be changing to . in the near future.

You can see what command-line options are available by running sbt "run-main GCDDriver --help" For example --target-dir will let you change the target directory