trilolil trilolil - 10 days ago 5
Linux Question

Why does "make all" seem to skip "all:" rule?

I am trying to analyze the following makefile and reproduce its "behavior" step by step.

Although I type "make all" it seems this makefile skips the "all:" line and jumps straight to "build/*.o" (hence the echo's).
The file and its corresponding output:

TOOLCHAIN ?= arm-none-eabi-

SOURCES = Demo/main.c \
Demo/startup.c \
Demo/Drivers/rpi_gpio.c \
Demo/Drivers/rpi_irq.c \
Source/tasks.c \
Source/list.c \
Source/portable/GCC/RaspberryPi/port.c \
Source/portable/GCC/RaspberryPi/portisr.c \
Source/portable/MemMang/heap_4.c

OBJECTS = $(patsubst %.c,build/%.o,$(SOURCES))

INCDIRS = Source/include Source/portable/GCC/RaspberryPi \
Demo/Drivers Demo/

CFLAGS = -Wall $(addprefix -I ,$(INCDIRS))
CFLAGS += -D RPI2
CFLAGS += -march=armv7-a -mtune=cortex-a7 -mfloat-abi=hard -mfpu=neon-vfpv4

ASFLAGS += -march=armv7-a -mcpu=cortex-a7 -mfpu=neon-vfpv4 -mfloat-abi=hard

LDFLAGS =

.PHONY: all clean

all: $(MOD_NAME)
echo "in all"

$(MOD_NAME): $(OBJECTS)
echo "in mod name"
ld -shared $(LDFLAGS) $< -o $@

build/%.o: %.c
echo -e "\nin build/*.o:*.c\n"
mkdir -p $(dir $@)
$(TOOLCHAIN)gcc -c $(CFLAGS) $< -o $@

build/%.o: %.s
echo -e "in build/*.o:*.s\n"
mkdir -p $(dir $@)
$(TOOLCHAIN)as $(ASFLAGS) $< -o $@

all: kernel7.list kernel7.img kernel7.syms kernel7.hex
echo -e"in kernel all\n"
$(TOOLCHAIN)size kernel7.elf


kernel7.img: kernel7.elf
$(TOOLCHAIN)objcopy kernel7.elf -O binary $@
echo -e "in kernel7.img\n"

kernel7.list: kernel7.elf
echo -e "kernel7.list\n"
$(TOOLCHAIN)objdump -D -S kernel7.elf > $@

kernel7.syms: kernel7.elf
echo -e "kernel7.syms\n"
$(TOOLCHAIN)objdump -t kernel7.elf > $@

kernel7.hex : kernel7.elf
echo -e "kernel7.hex\n"
$(TOOLCHAIN)objcopy kernel7.elf -O ihex $@

kernel7.elf: $(OBJECTS)
echo -e "kernel7.elf\n"
$(TOOLCHAIN)ld $^ -static -Map kernel7.map -o $@ -T Demo/raspberrypi.ld

clean:
rm -f $(OBJECTS)
rm -f kernel7.list kernel7.img kernel7.syms
rm -f kernel7.elf kernel7.hex kernel7.map
rm -rf build
echo -e "cleaning \n"


enter image description here

I tried to replicate this behaviour myself with a tiny piece of code. But it doesn't seem to work:

SOURCES = Demo/Drivers/rpi_irq.c \
Demo/Drivers/rpi_gpio.c


OBJECTS = $(patsubst %.c,build/%.o,$(SOURCES))


.PHONY: all clean

all: $(MOD_NAME)
echo "making all"$(SOURCES)

$(MOD_NAME): $(OBJECTS)
echo "MOD_NAME"

build/%.o:%.c
mkdir -p $(dir $@)
arm-none-eabi-gcc -march=armv7-a -mcpu=cortex-a7 -mfpu=neon-vfpv4 -mfloat-abi=har $< -o $@


As you can see thanks to the echo's my code just doesn't even build my source code. I'd expect it to go from all->MOD_NAME->build. (This is all the output I get)

enter image description here

So my questions are:


  • How does the makefile I am analyzing manage to go straight to build/*.o?

  • Why does my implementation, which I think should do the same doesn't even compile my source code?


Answer

The Makefile that you copied contains 2 rules for "all". The first depends on $(MOD_NAME) which might be empty.

The second rule depends on multiple files "kernel7.*" which themselves depend on "kernel7.elf". Finally "kernel7.elf" depends on $(OBJECTS). This last rule is responsible that all your source files will be compiled.

The first rule with $(MOD_NAME) does not need to cause any compilation at all.

In your own Makefile you only have a rule for "all" depending on $(MOD_NAME). If $(MOD_NAME) is empty in your Makefile as well, you do not have any dependency for "all" at all. If "all" does not depend on anything, no source files will be compiled.

To solve your problem you need to provide some content for $(MOD_NAME).

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