Aquaskyline Aquaskyline - 4 years ago 153
C Question

Fast popcount on Intel Xeon Phi

I'm implementing an ultra fast popcount on Intel Xeon® Phi®, as it's a performance hotspot of various bioinformatics software.

I've implemented five pieces of code,

#if defined(__MIC__)
#include <zmmintrin.h>
__attribute__((align(64))) static const uint32_t POPCOUNT_4bit[16] = {0, 1, 1, 2, 1, 2, 2, 3, 1, 2, 2, 3, 2, 3, 3, 4};
__attribute__((align(64))) static const uint32_t MASK_4bit[16] = {0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF, 0xF};
inline uint64_t vpu_popcount1(uint64_t* buf, size_t n) {
register size_t result = 0;
size_t i;
register const __m512i popcnt = _mm512_load_epi32((void*)POPCOUNT_4bit);
register const __m512i mask = _mm512_load_epi32((void*)MASK_4bit);
register __m512i total;
register __m512i shuf;

#pragma unroll(8)
for (i = 0; i < n; i+=8) {
shuf = _mm512_load_epi32(&buf[i]);
_mm_prefetch((const char *)&buf[i+256], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[i+64], _MM_HINT_T0); // vprefetch0
total = _mm512_setzero_epi32();

total = _mm512_add_epi32(_mm512_permutevar_epi32(_mm512_and_epi32(shuf, mask), popcnt), total);
total = _mm512_add_epi32(_mm512_permutevar_epi32(_mm512_and_epi32(_mm512_srli_epi32(shuf, 4), mask), popcnt), total);
total = _mm512_add_epi32(_mm512_permutevar_epi32(_mm512_and_epi32(_mm512_srli_epi32(shuf, 8), mask), popcnt), total);
total = _mm512_add_epi32(_mm512_permutevar_epi32(_mm512_and_epi32(_mm512_srli_epi32(shuf, 12), mask), popcnt), total);
total = _mm512_add_epi32(_mm512_permutevar_epi32(_mm512_and_epi32(_mm512_srli_epi32(shuf, 16), mask), popcnt), total);
total = _mm512_add_epi32(_mm512_permutevar_epi32(_mm512_and_epi32(_mm512_srli_epi32(shuf, 20), mask), popcnt), total);
total = _mm512_add_epi32(_mm512_permutevar_epi32(_mm512_and_epi32(_mm512_srli_epi32(shuf, 24), mask), popcnt), total);
total = _mm512_add_epi32(_mm512_permutevar_epi32(_mm512_and_epi32(_mm512_srli_epi32(shuf, 28), mask), popcnt), total);

/* Reduce add, which is analogous to SSSE3's PSADBW instruction,
is not implementated as a single instruction in VPUv1, thus
emulated by multiple instructions*/
result += _mm512_reduce_add_epi32(total);
}

return result;
}

__attribute__((align(64))) static const unsigned magic[] = {\
0x55555555, 0x55555555, 0x55555555, 0x55555555,\
0x55555555, 0x55555555, 0x55555555, 0x55555555,\
0x55555555, 0x55555555, 0x55555555, 0x55555555,\
0x55555555, 0x55555555, 0x55555555, 0x55555555,\
0x33333333, 0x33333333, 0x33333333, 0x33333333,\
0x33333333, 0x33333333, 0x33333333, 0x33333333,\
0x33333333, 0x33333333, 0x33333333, 0x33333333,\
0x33333333, 0x33333333, 0x33333333, 0x33333333,\
0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F,\
0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F,\
0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F,\
0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F, 0x0F0F0F0F,\
0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF,\
0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF,\
0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF,\
0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF,\
0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,\
0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,\
0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,\
0x0000FFFF, 0x0000FFFF, 0x0000FFFF, 0x0000FFFF,\
0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,\
0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,\
0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF,\
0x000000FF, 0x000000FF, 0x000000FF, 0x000000FF
};

inline uint64_t vpu_popcount2(uint64_t* buf, size_t n) {
register size_t result = 0;
size_t i;

register const __m512i B0 = _mm512_load_epi32((void*)(magic+0));
register const __m512i B1 = _mm512_load_epi32((void*)(magic+16));
register const __m512i B2 = _mm512_load_epi32((void*)(magic+32));
register const __m512i B3 = _mm512_load_epi32((void*)(magic+48));
register const __m512i B4 = _mm512_load_epi32((void*)(magic+64));
register __m512i total;
register __m512i shuf;

#pragma unroll(8)
for (i = 0; i < n; i+=8) {
shuf = _mm512_load_epi32(&buf[i]);
_mm_prefetch((const char *)&buf[i+512], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[i+64], _MM_HINT_T0); // vprefetch0
total = _mm512_sub_epi32(shuf, _mm512_and_epi32(B0, _mm512_srli_epi32(shuf,1)));
total = _mm512_add_epi32(_mm512_and_epi32(B1, total), _mm512_and_epi32(B1,_mm512_srli_epi32(total,2)));
total = _mm512_and_epi32(B2, _mm512_add_epi32(total, _mm512_srli_epi32(total,4)));
total = _mm512_and_epi32(B3, _mm512_add_epi32(total, _mm512_srli_epi32(total,8)));
total = _mm512_and_epi32(B4, _mm512_add_epi32(total, _mm512_srli_epi32(total,16)));

/* Reduce add, which is analogous to SSSE3's PSADBW instruction,
is not implementated as a single instruction in VPUv1, thus
emulated by multiple instructions*/
result += _mm512_reduce_add_epi32(total);
}

return result;
}

inline uint64_t vpu_popcount3(uint64_t* buf, size_t n) {
register size_t result = 0;
size_t i;

register const __m512i B0 = _mm512_load_epi32((void*)(magic+0));
register const __m512i B1 = _mm512_load_epi32((void*)(magic+16));
register const __m512i B2 = _mm512_load_epi32((void*)(magic+32));
register const __m512i B3 = _mm512_load_epi32((void*)(magic+48));
register const __m512i B4 = _mm512_load_epi32((void*)(magic+64));
register __m512i total;
register __m512i shuf;

#pragma unroll(4)
for (i = 0; i < n; i+=16) {
shuf = _mm512_load_epi32(&buf[i]);
result += _mm_countbits_64(buf[i+8]);
_mm_prefetch((const char *)&buf[i+512], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[i+576], _MM_HINT_T1); // vprefetch1
result += _mm_countbits_64(buf[i+9]);
_mm_prefetch((const char *)&buf[i+64], _MM_HINT_T0); // vprefetch0
_mm_prefetch((const char *)&buf[i+128], _MM_HINT_T0); // vprefetch0
total = _mm512_sub_epi32(shuf, _mm512_and_epi32(B0, _mm512_srli_epi32(shuf,1)));
result += _mm_countbits_64(buf[i+10]);
total = _mm512_add_epi32(_mm512_and_epi32(B1, total), _mm512_and_epi32(B1,_mm512_srli_epi32(total,2)));
result += _mm_countbits_64(buf[i+11]);
total = _mm512_and_epi32(B2, _mm512_add_epi32(total, _mm512_srli_epi32(total,4)));
result += _mm_countbits_64(buf[i+12]);
total = _mm512_and_epi32(B3, _mm512_add_epi32(total, _mm512_srli_epi32(total,8)));
result += _mm_countbits_64(buf[i+13]);
total = _mm512_and_epi32(B4, _mm512_add_epi32(total, _mm512_srli_epi32(total,16)));
result += _mm_countbits_64(buf[i+14]);

/* Reduce add, which is analogous to SSSE3's PSADBW instruction,
is not implementated as a single instruction in VPUv1, thus
emulated by multiple instructions*/
result += _mm512_reduce_add_epi32(total);
result += _mm_countbits_64(buf[i+15]);
}

return result;
}

/* Using VPU or SSE's machine intrinsic, CPUs not supporting SIMD
* will use compiler's implementation, the speed of which depends */
static inline size_t scalar_popcountu(unsigned *buf, size_t n) {
register size_t cnt = 0;
size_t i;
#pragma vector always
#pragma unroll(8)
for (i = 0; i < n; i++) {
cnt += _mm_countbits_32(buf[i]);
_mm_prefetch((const char *)&buf[i+512], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[i+64], _MM_HINT_T0); // vprefetch0
}
return cnt;
}

static inline size_t scalar_popcountlu(uint64_t *buf, size_t n) {
register size_t cnt = 0;
size_t i;
#pragma vector always
#pragma unroll(8)
for (i = 0; i < n; i++) {
cnt += _mm_countbits_64(buf[i]);
_mm_prefetch((const char *)&buf[i+512], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[i+64], _MM_HINT_T0); // vprefetch0
}
return cnt;
}
#endif


A wrap up of the code with OpenMP support can be downloaded from https://www.dropbox.com/sh/b3sfqps19wa2oi4/iFQ9wQ1NTg

The code was compiled using Intel C/C++ Compiler XE 13 using command:

icc -debug inline-debug-info -O3 -mmic -fno-alias -ansi-alias -opt-streaming-stores always -ipo popcnt-mmic.cpp -o popcnt-mmic -vec-report=2 -openmp


The code runs natively on the co-processor (61 cores) with "122 threads" and thread affinity as "balanced" using exports:

export OMP_NUM_THREADS=122;export KMP_AFFINITY=balanced


I'm using Xeon Phi SE10p, B1 stepping, CentOS6.4
Testing on 28 megabytes of junks (filled by rand()) and iterate for 10000 times, the performance are as follows:

Buffer allocated at: 0x7f456b000000
OpenMP scalar_popcountu 4310169 us; cnt = 28439328
OpenMP scalar_popcountlu 1421139 us; cnt = 28439328
OpenMP vpu_popcount 1489992 us; cnt = 28439328
OpenMP vpu_popcount2 1109530 us; cnt = 28439328
OpenMP vpu_popcount3 951122 us; cnt = 28439328


The "scalar_popcountu" and "scalar_popcountlu" use "_mm_countbits_32" and "_mm_countbits_64" intrinsics respectively, which utilize the scalar "popcnt" instruction. Setting "#pragma vector always" asks to compiler to vectorize the load and sum as 16 unsigned ints or 8 unsigned longs a time, although the popcount itself is still a scalar instruction.

The implementation of vpu_popcount1 is analogous to the SSSE3 popcount implementation http://wm.ite.pl/articles/sse-popcount.html. However, 1) Xeon Phi does not support packed byte operations on integer (the minimum is double words, aka 32-bit) and 2) it does not implement the "Packed sum of absolute difference" instruction (like _mm_sad_epu8 in SSSE3), thus the reduction add was performed by a combination of four groups of "vpermf32x4", "vpaddd" and "movslq". Thus the implementation generated much more instructions than the original SSSE3 version.

The implementation of vpu_popcount2 is analogous to the SSE2 popcount implementation (one can refer to "Hacker's Delight"). The implementation generates fewer instructions than vpu_popcount1 and is about 30% faster. However, the tedious "reduce add" still cannot be avoided.

The implementation of vpu_popcount3 is very Xeon Phi specific. With the mixture of vector and scalar operations, it's about 15% faster than vpu_popcount2 (the intersperse of scalar operations amid vector operations is leisure in my implementation, one can rearrange the scalar operations according to assembly code generated by the compiler, but the expected improvement is limited as far as i'm concerned). The improvement is base on the observation that 1) Xeon Phi is in-order scheduling, 2) two scalar instructions or "1 vector+ 1 scalar" instructions can be issued per clock cycle. I've decrease the unroll from 8 to 4 to avoid register file saturation.

The explicit prefetch from memory to L2 8 loops in advance and from L2 to L1 1 loops in advance in each function has increased the L1 Hit Ratio from 0.38 to 0.994.

The unroll do increase the performance by about 15%. This is counter intuitive since Xeon Phi is in-order scheduling. But unroll enables the icc compiler to do as much compile time scheduling as possible.

Do we have even more technics to boost the performance?

Two piece of faster codes from Brian Nickerson,

OpenMP vpu_popcount2 1110737 us; cnt = 28439328
OpenMP vpu_popcount3 951459 us; cnt = 28439328
OpenMP vpu_popcount3_r 815126 us; cnt = 28439328
OpenMP vpu_popcount5 746852 us; cnt = 28439328


vpu_popcount3_revised:

inline uint64_t vpu_popcount3_revised(uint64_t* buf, size_t n) {
_mm_prefetch((const char *)&buf[0], _MM_HINT_T0); // vprefetch0
_mm_prefetch((const char *)&buf[8], _MM_HINT_T0); // vprefetch0
_mm_prefetch((const char *)&buf[16], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[24], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[32], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[40], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[48], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[56], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[64], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[72], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[80], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[88], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[96], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[104], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[112], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[120], _MM_HINT_T1); // vprefetch1
register size_t result;
size_t i;

register const __m512i B0 = _mm512_load_epi32((void*)(magic+0));
register const __m512i B1 = _mm512_load_epi32((void*)(magic+16));
register const __m512i B2 = _mm512_load_epi32((void*)(magic+32));
register const __m512i B3 = _mm512_load_epi32((void*)(magic+48));
register const __m512i B4 = _mm512_load_epi32((void*)(magic+64));
register __m512i total0;
register __m512i total1;
register __m512i shuf0;
register __m512i shuf1;
register __m512i result0;
register __m512i result1;

result0 = _mm512_setzero_epi32();
result1 = _mm512_setzero_epi32();

for (i = 0; i < n; i+=16) {
shuf0 = _mm512_load_epi32(&buf[i ]);
shuf1 = _mm512_load_epi32(&buf[i+8]);
_mm_prefetch((const char *)&buf[i+128], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[i+136], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[i+16], _MM_HINT_T0); // vprefetch0
_mm_prefetch((const char *)&buf[i+24], _MM_HINT_T0); // vprefetch0
total0 = _mm512_sub_epi32(shuf0, _mm512_and_epi32(B0, _mm512_srli_epi32(shuf0,1)));
total1 = _mm512_sub_epi32(shuf1, _mm512_and_epi32(B0, _mm512_srli_epi32(shuf1,1)));
total0 = _mm512_add_epi32(_mm512_and_epi32(B1, total0), _mm512_and_epi32(B1,_mm512_srli_epi32(total0,2)));
total1 = _mm512_add_epi32(_mm512_and_epi32(B1, total1), _mm512_and_epi32(B1,_mm512_srli_epi32(total1,2)));
total0 = _mm512_and_epi32(B2, _mm512_add_epi32(total0, _mm512_srli_epi32(total0,4)));
total1 = _mm512_and_epi32(B2, _mm512_add_epi32(total1, _mm512_srli_epi32(total1,4)));
total0 = _mm512_and_epi32(B3, _mm512_add_epi32(total0, _mm512_srli_epi32(total0,8)));
total1 = _mm512_and_epi32(B3, _mm512_add_epi32(total1, _mm512_srli_epi32(total1,8)));
total0 = _mm512_and_epi32(B4, _mm512_add_epi32(total0, _mm512_srli_epi32(total0,16)));
total1 = _mm512_and_epi32(B4, _mm512_add_epi32(total1, _mm512_srli_epi32(total1,16)));
result0 = _mm512_add_epi32(result0,total0);
result1 = _mm512_add_epi32(result1,total1);

}

result0 = _mm512_add_epi32(result0,result1);
result = _mm512_reduce_add_epi32(result0);

return result;
}


vpu_popcount5:

inline uint64_t vpu_popcount5(uint64_t* buf, size_t n) {
_mm_prefetch((const char *)&buf[0], _MM_HINT_T0); // vprefetch0
_mm_prefetch((const char *)&buf[8], _MM_HINT_T0); // vprefetch0
_mm_prefetch((const char *)&buf[16], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[24], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[32], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[40], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[48], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[56], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[64], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[72], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[80], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[88], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[96], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[104], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[112], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[120], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[128], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[136], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[144], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[152], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[160], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[168], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[176], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[184], _MM_HINT_T1); // vprefetch1
register size_t result;
size_t i;

register const __m512i B0 = _mm512_load_epi32((void*)(magic+0));
register const __m512i B1 = _mm512_load_epi32((void*)(magic+16));
register const __m512i B2 = _mm512_load_epi32((void*)(magic+32));
register const __m512i B3 = _mm512_load_epi32((void*)(magic+48));
register const __m512i B4 = _mm512_load_epi32((void*)(magic+64));
register const __m512i B6 = _mm512_load_epi32((void*)(magic+80));
register __m512i total0;
register __m512i total1;
register __m512i total2;
register __m512i total3;
register __m512i shuf0;
register __m512i shuf1;
register __m512i shuf2;
register __m512i shuf3;
register __m512i result0;
register __m512i result1;

result0 = _mm512_setzero_epi32();
result1 = _mm512_setzero_epi32();

for (i = 0; i < n; i+=32) {
shuf0 = _mm512_load_epi32(&buf[i ]);
shuf1 = _mm512_load_epi32(&buf[i+ 8]);
shuf2 = _mm512_load_epi32(&buf[i+16]);
shuf3 = _mm512_load_epi32(&buf[i+24]);
_mm_prefetch((const char *)&buf[i+192], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[i+200], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[i+208], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[i+216], _MM_HINT_T1); // vprefetch1
_mm_prefetch((const char *)&buf[i+32], _MM_HINT_T0); // vprefetch0
_mm_prefetch((const char *)&buf[i+40], _MM_HINT_T0); // vprefetch0
_mm_prefetch((const char *)&buf[i+48], _MM_HINT_T0); // vprefetch0
_mm_prefetch((const char *)&buf[i+56], _MM_HINT_T0); // vprefetch0
total0 = _mm512_sub_epi32(shuf0, _mm512_and_epi32(B0, _mm512_srli_epi32(shuf0,1))); // max value in nn is 10
total1 = _mm512_sub_epi32(shuf1, _mm512_and_epi32(B0, _mm512_srli_epi32(shuf1,1)));
total2 = _mm512_sub_epi32(shuf2, _mm512_and_epi32(B0, _mm512_srli_epi32(shuf2,1)));
total3 = _mm512_sub_epi32(shuf3, _mm512_and_epi32(B0, _mm512_srli_epi32(shuf3,1)));
total0 = _mm512_add_epi32(_mm512_and_epi32(B1, total0), _mm512_and_epi32(B1,_mm512_srli_epi32(total0,2))); // max value in nnnn is 0100
total1 = _mm512_add_epi32(_mm512_and_epi32(B1, total1), _mm512_and_epi32(B1,_mm512_srli_epi32(total1,2)));
total2 = _mm512_add_epi32(_mm512_and_epi32(B1, total2), _mm512_and_epi32(B1,_mm512_srli_epi32(total2,2)));
total3 = _mm512_add_epi32(_mm512_and_epi32(B1, total3), _mm512_and_epi32(B1,_mm512_srli_epi32(total3,2)));
total0 = _mm512_and_epi32(B2, _mm512_add_epi32(total0, _mm512_srli_epi32(total0,4))); // max value in 0000nnnn is 00001000
total1 = _mm512_and_epi32(B2, _mm512_add_epi32(total1, _mm512_srli_epi32(total1,4)));
total2 = _mm512_and_epi32(B2, _mm512_add_epi32(total2, _mm512_srli_epi32(total2,4)));
total3 = _mm512_and_epi32(B2, _mm512_add_epi32(total3, _mm512_srli_epi32(total3,4)));
total0 = _mm512_add_epi32(total0, total1); // max value in 000nnnnn is 00010000
total1 = _mm512_add_epi32(total2, total3);
total0 = _mm512_add_epi32(total0, _mm512_srli_epi32(total0,8)); // max value in xxxxxxxx00nnnnnn is 00100000
total1 = _mm512_add_epi32(total1, _mm512_srli_epi32(total1,8));
total0 = _mm512_and_epi32(B6, _mm512_add_epi32(total0, _mm512_srli_epi32(total0,16))); // max value in each element is 01000000, i.e. 64
total1 = _mm512_and_epi32(B6, _mm512_add_epi32(total1, _mm512_srli_epi32(total1,16)));
result0 = _mm512_add_epi32(result0,total0);
result1 = _mm512_add_epi32(result1,total1);
}

result0 = _mm512_add_epi32(result0,result1);
result = _mm512_reduce_add_epi32(result0);

return result;
}

Answer Source

Since posting yesterday, I have been able to run your code and my suggestion on my own card. I do not get exactly the same timings as you, probably due to the stepping of my hardware, and perhaps related to the versions of my compiler. But the trend holds up, and my suggestion seemed to attain about a fifteen percent performance boost.

I got an additional small performance boost, between five and ten percent, with a little more tweaking, as shown in the code below. Please note that in the following code snippet, B6 has each element set to 0x000000FF. At this point, I think the algorithm might be pressing up pretty close to the maximum sustainable bandwidth deliverable from GDDR to the L2 cache.

(ADDED NOTE: A testament to this assertion is that if I wrap the body of the popcount5 function with a for loop that repeats it ten times -- and note that this is ten rapid repetitions of the "chunk_size" of input data, so nine of the times it will be sizzling hot in L2 -- the total time for the test increases by only a factor of about five, rather than ten. I bring this up because I THINK your goal is to tune the speed of the bit count logic, but perhaps the application in which you hope to deploy it actually has a smaller and/or hotter working set. If that is so, throttling introduced by DRAM-->L2 bandwidth is fogging the picture. But note that ratcheting back the size of your test input so that it tends to stay hotter in L2 seems to cause other overhead -- probably the openmp overhead -- to become relatively more significant.)

inline uint64_t vpu_popcount5(uint64_t* buf, size_t n)  {
    _mm_prefetch((const char *)&buf[0], _MM_HINT_T0); // vprefetch0
    _mm_prefetch((const char *)&buf[8], _MM_HINT_T0); // vprefetch0
    _mm_prefetch((const char *)&buf[16], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[24], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[32], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[40], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[48], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[56], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[64], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[72], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[80], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[88], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[96], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[104], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[112], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[120], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[128], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[136], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[144], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[152], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[160], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[168], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[176], _MM_HINT_T1); // vprefetch1
    _mm_prefetch((const char *)&buf[184], _MM_HINT_T1); // vprefetch1
    register size_t result;
    size_t i;

    register const __m512i B0 = _mm512_load_epi32((void*)(magic+0));
    register const __m512i B1 = _mm512_load_epi32((void*)(magic+16));
    register const __m512i B2 = _mm512_load_epi32((void*)(magic+32));
    register const __m512i B6 = _mm512_load_epi32((void*)(magic+80));
    register __m512i total0;
    register __m512i total1;
    register __m512i total2;
    register __m512i total3;
    register __m512i shuf0;
    register __m512i shuf1;
    register __m512i shuf2;
    register __m512i shuf3;
    register __m512i result0;
    register __m512i result1;

    result0 = _mm512_setzero_epi32();
    result1 = _mm512_setzero_epi32();

    for (i = 0; i < n; i+=32) {
        shuf0 = _mm512_load_epi32(&buf[i   ]);
        shuf1 = _mm512_load_epi32(&buf[i+ 8]);
        shuf2 = _mm512_load_epi32(&buf[i+16]);
        shuf3 = _mm512_load_epi32(&buf[i+24]);
        _mm_prefetch((const char *)&buf[i+192], _MM_HINT_T1); // vprefetch1
        _mm_prefetch((const char *)&buf[i+200], _MM_HINT_T1); // vprefetch1
        _mm_prefetch((const char *)&buf[i+208], _MM_HINT_T1); // vprefetch1
        _mm_prefetch((const char *)&buf[i+216], _MM_HINT_T1); // vprefetch1
        _mm_prefetch((const char *)&buf[i+32], _MM_HINT_T0); // vprefetch0
        _mm_prefetch((const char *)&buf[i+40], _MM_HINT_T0); // vprefetch0
        _mm_prefetch((const char *)&buf[i+48], _MM_HINT_T0); // vprefetch0
        _mm_prefetch((const char *)&buf[i+56], _MM_HINT_T0); // vprefetch0
        total0 = _mm512_sub_epi32(shuf0, _mm512_and_epi32(B0, _mm512_srli_epi32(shuf0,1)));                        //  max value in nn is 10
        total1 = _mm512_sub_epi32(shuf1, _mm512_and_epi32(B0, _mm512_srli_epi32(shuf1,1)));
        total2 = _mm512_sub_epi32(shuf2, _mm512_and_epi32(B0, _mm512_srli_epi32(shuf2,1)));
        total3 = _mm512_sub_epi32(shuf3, _mm512_and_epi32(B0, _mm512_srli_epi32(shuf3,1)));
        total0 = _mm512_add_epi32(_mm512_and_epi32(B1, total0), _mm512_and_epi32(B1,_mm512_srli_epi32(total0,2))); //  max value in nnnn is 0100
        total1 = _mm512_add_epi32(_mm512_and_epi32(B1, total1), _mm512_and_epi32(B1,_mm512_srli_epi32(total1,2)));
        total2 = _mm512_add_epi32(_mm512_and_epi32(B1, total2), _mm512_and_epi32(B1,_mm512_srli_epi32(total2,2)));
        total3 = _mm512_add_epi32(_mm512_and_epi32(B1, total3), _mm512_and_epi32(B1,_mm512_srli_epi32(total3,2)));
        total0 = _mm512_and_epi32(B2, _mm512_add_epi32(total0, _mm512_srli_epi32(total0,4)));                      //  max value in 0000nnnn is 00001000
        total1 = _mm512_and_epi32(B2, _mm512_add_epi32(total1, _mm512_srli_epi32(total1,4)));
        total2 = _mm512_and_epi32(B2, _mm512_add_epi32(total2, _mm512_srli_epi32(total2,4)));
        total3 = _mm512_and_epi32(B2, _mm512_add_epi32(total3, _mm512_srli_epi32(total3,4)));
        total0 = _mm512_add_epi32(total0, total1);                                                                 //  max value in 000nnnnn is 00010000
        total1 = _mm512_add_epi32(total2, total3);
        total0 = _mm512_add_epi32(total0, _mm512_srli_epi32(total0,8));                                            //  max value in xxxxxxxx00nnnnnn is 00100000
        total1 = _mm512_add_epi32(total1, _mm512_srli_epi32(total1,8));
        total0 = _mm512_and_epi32(B6, _mm512_add_epi32(total0, _mm512_srli_epi32(total0,16)));                     //  max value in each element is 01000000, i.e. 64
        total1 = _mm512_and_epi32(B6, _mm512_add_epi32(total1, _mm512_srli_epi32(total1,16)));
        result0 = _mm512_add_epi32(result0,total0);
        result1 = _mm512_add_epi32(result1,total1);

        /* Reduce add, which is analogous to SSSE3's PSADBW instruction,
           is not implementated as a single instruction in VPUv1, thus
           emulated by multiple instructions*/
    }

    result0 = _mm512_add_epi32(result0,result1);
    result  = _mm512_reduce_add_epi32(result0);

    return result;
}
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